Recently, a field effect transistor employing a metal gate electrode made of an alloy material such as a silicided metal has gathered attention. This field effect transistor employing a metal gate electrode has an advantage that it reduces a compound capacity by eliminating depletion in a gate electrode and facilitates control of a Vth (threshold voltage) by controlling a work function.
Conventionally, there has been used a semiconductor device comprising an N-type field effect transistor (hereinafter, referred to as an “NMOS transistor”) and a P-type field effect transistor (hereinafter, referred to as a “PMOS transistor”) in which gate electrodes of these MOS transistors are combined to be a single line electrode. In this semiconductor device, the sections of the line electrode over the N-type and P-type areas formed within the semiconductor substrate correspond to the gate electrodes in each MOS transistor, respectively.
Here, the NMOS transistor and the PMOS transistor are different in properties in terms of the relationship between a work function of the material for the gate electrode and a Vth of the MOS transistor. In a semiconductor device in which an NMOS and a PMOS transistors are connected as a single line, it is, therefore, necessary to individually optimize a Vth of each MOS transistor by forming sections of the line electrode corresponding to gate electrodes of each MOS transistor from different materials and controlling a work function of the material of each gate electrode.
Thus, a semiconductor device in which gate electrodes for an NMOS and a PMOS transistors are made of different materials has been investigated. Japanese Laid-open Patent Publication No. 2005-167251 (reference 1) has disclosed a semiconductor device in which an NMOS transistor and a PMOS transistor are made of different silicide materials. This semiconductor device is prepared by depositing a first and a second metal-containing layers on polysilicon regions to be an NMOS and a PMOS transistors, respectively, and siliciding the polysilicon regions to be an NMOS and a PMOS transistors at one time by heating.
In addition, Japanese Laid-open Patent Publication No. 2004-221226 (reference 2) has disclosed a semiconductor device in which an NMOS transistor and a PMOS transistor are made of different silicide materials. This semiconductor device can be prepared mainly by one of the following two processes. In a first process, a gate electrode for a first MOS transistor is formed by preheating at a high temperature and then a gate electrode for a second MOS transistor is formed by processing at a low temperature. In a second process, after forming a polysilicon region comprising of two regions containing dopants of different elements from each other, it is silicided at one time by heating, to form the gate electrodes for each MOS transistor.
However, in a semiconductor device according to Japanese Laid-open Patent Publication No. 2005-167251 (reference 1), gate electrodes in an NMOS and a PMOS transistors are simultaneously formed at one time by heating, so that a gate electrode material (a constituent element of a gate electrode) having a larger reaction rate or diffusion coefficient infiltrates the other gate electrode area, leading to a nonuniform composition of the gate electrode. Furthermore, this manufacturing process cannot produce gate electrodes for each MOS transistor under the optimal conditions for the gate electrodes material for the NMOS and the PMOS transistors.
In a semiconductor device according to Japanese Laid-open Patent Publication No. 2004-221226 (reference 2), the first process, when first siliciding a gate pattern 41 on a first MOS transistor as shown in FIG. 1(a), may provide a compositionally nonuniform transition layer 42 due to diffusion of a diffusing species (a constituent element having a larger diffusion coefficient) constituting the gate pattern to the gate pattern over a second MOS transistor. As a result, even after siliciding a gate pattern 43 over the second MOS transistor, the transition layer 42 remains and thus a gate electrode having a uniform composition cannot be formed (FIG. 1(b)). Furthermore, in the second process, due to difference in a diffusion coefficient between dopants contained in two regions 44 and 45 in a polysilicon (FIG. 1(c)), a dopant present in one region infiltrates the other region during heating (siliciding), and thus a gate electrode having a uniform composition cannot be formed (FIG. 1(d)).
Thus, in the semiconductor devices according to Laid-open Patent Publication Nos. 2005-167251 and 2004-221226 (references 1 and 2), a gate electrode composition in each MOS transistor is nonuniform, so that the gate electrode material has a work function deviated from a desired value. Consequently, a desired Vth (threshold voltage) cannot be achieved, leading to an uncontrolled Vth. Such a problem is caused by the fact that the materials of the gate electrodes in each MOS transistor are close to each other, during forming a gate electrode (heating), mutual diffusion between the gate electrode materials occurs, and a gate electrode material (a constituent element of a gate electrode) has diffused from one region to the other region to give a transition layer 42 (FIG. 2(a), (b)).
In view of the above problems, the present invention is characterized in that as shown in FIG. 2(c), a diffusion barrier region capable of preventing diffusion of a gate electrode material constituting each MOS transistor is formed between gate electrode sections for an NMOS transistor and PMOS transistor in a line electrode. Furthermore, an objective of the present invention is to provide a semiconductor device in which each MOS transistor has a uniform gate electrode composition by preventing diffusion of a gate electrode material in each MOS transistor by a diffusion barrier region. Thus, another objective is to provide a semiconductor device exhibiting excellent operation properties by preventing deviation in a work function of a gate electrode material to effectively control a Vth.